At the European 3D TSV Summit in Grenoble, France on January 22-23, 2013, imec, a world-leading nano-electronics research institute, announced that together with Cadence Design Systems they have developed, implemented and validated an automated 3D Design-for-Test (DFT) solution to test logic-memory interconnects in DRAM-on-logic stacks. The solution, based on Cadence Encounter Test technology, was verified on an industrial test chip containing a logic die and a JEDEC-compliant Wide-I/O Mobile DR...